Symbolic Simulation Methods for Industrial Formal Verification
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Symbolic Simulation Methods for Industrial Formal Verification contains two distinct, but related, approaches to the verification problem. Both are based on symbolic simulation. The first approach is applied at the gate level and has been successful in verifying sub-circuits of industrial microprocessors with tens and even hundreds of thousands of gates. The second approach is applied at a high-level of abstraction and is used for high-level descriptions of designs.The book contains three main topics:Self consistency, a technique for deriving a formal specification of design behavior from the ...
Symbolic Simulation Methods for Industrial Formal Verification contains two distinct, but related, approaches to the verification problem. Both are based on symbolic simulation. The first approach is applied at the gate level and has been successful in verifying sub-circuits of industrial microprocessors with tens and even hundreds of thousands of gates. The second approach is applied at a high-level of abstraction and is used for high-level descriptions of designs.
The book contains three main topics:
Self consistency, a technique for deriving a formal specification of design behavior from the design itself; The use of the parametric representation to encode predicates as functional vectors for symbolic simulation, an important step in addressing the state-explosion problem; Incremental flushing, a method used to verify high-level descriptions of out-of-order execution.Symbolic Simulation Methods for Industrial Formal Verification concludes with work on verification of simplified models of out-of-order processors.
The book contains three main topics:
Self consistency, a technique for deriving a formal specification of design behavior from the design itself; The use of the parametric representation to encode predicates as functional vectors for symbolic simulation, an important step in addressing the state-explosion problem; Incremental flushing, a method used to verify high-level descriptions of out-of-order execution.Symbolic Simulation Methods for Industrial Formal Verification concludes with work on verification of simplified models of out-of-order processors.
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