Semiconductor Memory Testing
Fault Models and Test Considerations for High Performance Embedded SRAM's
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Stringent test quality requirements, at-speed test limitations & total cost associated with using expensive off-chip testers for embedded memory testing have forced system designers to introduce on-chip Memory Built-in Self Test (MBIST) techniques to generate, apply, read and compares test patterns in order to expose subtle defects of SRAM''s. The book discusses in detail the various fault models and test requirements associated with embedded SRAM s in today s System-On-Chip s and focuses on the implementation of testing algorithms for embedded SRAMs in the MBIST engine. The book also discusse...
Stringent test quality requirements, at-speed test limitations & total cost associated with using expensive off-chip testers for embedded memory testing have forced system designers to introduce on-chip Memory Built-in Self Test (MBIST) techniques to generate, apply, read and compares test patterns in order to expose subtle defects of SRAM''s. The book discusses in detail the various fault models and test requirements associated with embedded SRAM s in today s System-On-Chip s and focuses on the implementation of testing algorithms for embedded SRAMs in the MBIST engine. The book also discusses a finding where failure analysis and silicon debug required an update to the algorithms and pattern backgrounds implemented in the MBIST.
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