SATH: Simulated Annealing C code To FPGA Hardware compiler
Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
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A tool flow is presented for deriving acceleratorcircuits on an FPGA from ANSI C source code by exploring architecturesolutions that conform to a preset template through scheduling andmapping algorithms. A case study carried out on simulatedannealing-based scheduling software used for spacecraft systems isexplained. The goal of the tool is the derivation of a design thatmaximizes throughput while minimizing footprint. Results obtained arecompared with a peer C to RTL tool, a space-borne embedded processor and acommoditydesktop processor for a variety of problems.
A tool flow is presented for deriving accelerator
circuits on an FPGA
from ANSI C source code by exploring architecture
solutions that
conform to a preset template through scheduling and
mapping
algorithms. A case study carried out on simulated
annealing-based
scheduling software used for spacecraft systems is
explained. The goal
of the tool is the derivation of a design that
maximizes throughput
while minimizing footprint. Results obtained are
compared with a peer
C to RTL tool, a space-borne embedded processor and a
commodity
desktop processor for a variety of problems.
circuits on an FPGA
from ANSI C source code by exploring architecture
solutions that
conform to a preset template through scheduling and
mapping
algorithms. A case study carried out on simulated
annealing-based
scheduling software used for spacecraft systems is
explained. The goal
of the tool is the derivation of a design that
maximizes throughput
while minimizing footprint. Results obtained are
compared with a peer
C to RTL tool, a space-borne embedded processor and a
commodity
desktop processor for a variety of problems.
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