Reference-Ladder Free Flash Analog to Digital Converter Architecture
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Document from the year 2021 in the subject Computer Science - Programming, grade: 10, Manipal University Jaipur, language: English, abstract: In this book, the primary research objective is to design a novel comparator to get rid-off reference-ladder circuit. The design of power efficient Flash ADC is investigated by utilizing a novel power optimized single-ended comparator. The proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage generation method for producing the reference voltage for the Flash ADC design. By employing optimized comparato...
Document from the year 2021 in the subject Computer Science - Programming, grade: 10, Manipal University Jaipur, language: English, abstract: In this book, the primary research objective is to design a novel comparator to get rid-off reference-ladder circuit. The design of power efficient Flash ADC is investigated by utilizing a novel power optimized single-ended comparator. The proposed comparator generates inherent embedded threshold voltage. It uses the variable threshold voltage generation method for producing the reference voltage for the Flash ADC design. By employing optimized comparator, the Flash ADC achieves various benefits, as it does not require the necessity of a reference resistor ladder as well as front-end track and hold circuit. This reduces both layout area and power consumption and makes it appropriate for System-on-Chip (SoC) ADC implementation . The basic structure of the single-ended comparator is modified CMOS Inverter. The performance of modified CMOS Inverter circuit is compared with the static CMOS Inverter. To demonstrate the functionality of the new comparator, 4-bit and 6-bit Flash ADCs has been designed and simulated under the environment of Cadence and LTspice CAD tools. For both of the Flash ADCs, a comparative analysis is presented with previously published works on Flash ADCs. The secondary research objective is to propose a novel power reduction technique for high-speed Flash analog-to-digital converter, which not only reduces the power consumption in comparator but also examines the inactive comparators in the Flash ADC, thus inactive comparators get shutdown to save the unnecessary power consumption.This approach is based on two-step method of data conversion. By this method the total numbers of active comparators are reduced in comparison with the conventional Flash ADC. This feature of active comparators reduces the overall power consumption of the converter and the resultant architecture develops into power efficient Flash ADC architecture.
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