Reduced Thermal Processing for ULSI
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As feature dimensions of integrated circuits shrink, the associated geometrical constraints on junction depth impose severe restrictions on the thermal budget for processing such devices. Furthermore, due to the relatively low melting point of the first aluminum metallization level, such restrictions extend to the fabrication of multilevel structures that are now essential in increasing packing density of interconnect lines. The fabrication of ultra large scale integrated (ULSI) devices under thermal budget restrictions requires the reassessment of existing and the development of new microelec...
As feature dimensions of integrated circuits shrink, the associated geometrical constraints on junction depth impose severe restrictions on the thermal budget for processing such devices. Furthermore, due to the relatively low melting point of the first aluminum metallization level, such restrictions extend to the fabrication of multilevel structures that are now essential in increasing packing density of interconnect lines. The fabrication of ultra large scale integrated (ULSI) devices under thermal budget restrictions requires the reassessment of existing and the development of new microelectronic materials and processes. This book addresses three broad but interrelated areas. The first area focuses on the subject of rapid thermal processing (RTP), a technology that allows minimization of processing time while relaxing the constraints on high temperature. Initially developed to limit dopant redistribution, current applications of RTP are shown here to encompass annealing, oxidation, nitridation, silicidation, glass reflow, and contact sintering. In a second but complementary area, advances in equipment design and performance of rapid thermal processing equipment are presented in conjunction with associated issues of temperature measurement and control. Defect mechanisms are assessed together with the resulting properties of rapidly deposited and processed films. The concept of RTP integration for a full CMOS device process is also examined together with its impact on device characteristics.
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