Reconfiguration is Shared Memory
Collapsing the Hierarchy of Parallel Models with Reconfigurable Buses and Shared Memory
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Many models of parallel computation have been developed over the years. Models with shared memory are useful for deriving strong lower bounds, and have also been implemented recently. Models with reconfigurable buses have proven an excellent model for VLSI circuit design and are also easily implementable in VLSI. The hierarchy of either model has not been established completely, and the two models have not been related to each other. In this work we first collapse the hierarchy of reconfiguration, showing that Collision can simulate all the conflict resolution rules including the unrealistic b...
Many models of parallel computation have been developed over the years. Models with shared memory are useful for deriving strong lower bounds, and have also been implemented recently. Models with reconfigurable buses have proven an excellent model for VLSI circuit design and are also easily implementable in VLSI. The hierarchy of either model has not been established completely, and the two models have not been related to each other. In this work we first collapse the hierarchy of reconfiguration, showing that Collision can simulate all the conflict resolution rules including the unrealistic but convenient Combining. We also collapse the hierarchy of shared memory, showing that the convenient but unrealistic Broadcast instruction does not add computational power. We then show that shared memory and reconfiguration are in fact equivalent. This simplifies greatly the area of parallel algorithms. Beside the obvious use for researchers in the area of parallel models, our work offers strong support for converting algorithms and techniques between shared memory and reconfigurable buses, and also for practitioners implementing PRAM models and algorithms or working on VLSI design.
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