Reconfigurable Transform Architecture for Multiple Video Codecs
Implementation of a low cost unified integer DCT architecture for four video codec: AVS, VC-1, H.264/AVC and HEVC
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This book presents a cost-shared architecture to compute multiple integer discrete cosine transform (Int-DCT) of four video codecs: AVS, VC-1, H.264/AVC and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized ''decompose and share'' algorithm to compute both 4x4 and 8x8 Int-DCT. The algorithm is later applied to the video codecs. The hardware share approach ensures maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significant...
This book presents a cost-shared architecture to compute multiple integer discrete cosine transform (Int-DCT) of four video codecs: AVS, VC-1, H.264/AVC and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized ''decompose and share'' algorithm to compute both 4x4 and 8x8 Int-DCT. The algorithm is later applied to the video codecs. The hardware share approach ensures maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18um technology. The results show significant reduction in hardware cost and meet the requirements of real time video coding applications.
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