Quantum Ballistic Simulation of Nanoscale Double Gate MOSFET
Performance Improvement Using High-k Gate Stack
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The scaling of MOSFETs as dictated by the ITRS has continued unabated for many years and enabled the worldwide semiconductor market to grow at a phenomenal rate. However, the ITRS scaling is reaching hard limitations. One of the most significant problems is the maintenance of electrostatic integrity, which demands the use of extremely thin gate oxides to provide the required high gate capacitance, as well as the use of high channel doping to control short channel effects. These requirements lead to low device performance and tunneling current becomes quite prominent. This book introduces a pro...
The scaling of MOSFETs as dictated by the ITRS has continued unabated for many years and enabled the worldwide semiconductor market to grow at a phenomenal rate. However, the ITRS scaling is reaching hard limitations. One of the most significant problems is the maintenance of electrostatic integrity, which demands the use of extremely thin gate oxides to provide the required high gate capacitance, as well as the use of high channel doping to control short channel effects. These requirements lead to low device performance and tunneling current becomes quite prominent. This book introduces a promising solution to these problems, that is Double Gate MOSFET with high-k gate stack. This book provides an elaborate performance analysis of DG MOSFET with high-k material on both top and bottom gate stack in terms of drain current & subthreshold characteristics using 2D quantum simulator nanoMOS 4.0.
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