Power- And Thermal-Aware Testing of System-on-Chip
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Testing is the most crucial part of VLSI Design cycle, which evaluates the quality and defect-free functionality of an integrated circuit. Exponentially growing design complexity demands for an enormous amount of test data to test an IC for different possible faults. The demand of shorter design turnaround time often encourages the test engineers to test multiple modules concurrently, helping to reduce the overall test time. On the other hand, overlapping testing of multiple modules increases the power consumption and temperature manifold, which in turn, may cause serious damage to the chip du...
Testing is the most crucial part of VLSI Design cycle, which evaluates the quality and defect-free functionality of an integrated circuit. Exponentially growing design complexity demands for an enormous amount of test data to test an IC for different possible faults. The demand of shorter design turnaround time often encourages the test engineers to test multiple modules concurrently, helping to reduce the overall test time. On the other hand, overlapping testing of multiple modules increases the power consumption and temperature manifold, which in turn, may cause serious damage to the chip due to overheating and burning. An efficient test scheduling strategy plays a vital role to meet the criteria of low power and temperature simultaneously with lower test time. This book discusses different problems arise due to high test mode power and temperature and viable solutions to reduce test time without violating the system level power and temperature tolerance limits. It also discusses thermal-safe strategies to store the enormous amount of test data in a compressed manner to reduce the storage cost as well as the temperature of the chip.
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