Networks on Chip
Topology, Switching, Routing
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Network-on-Chip (NoC) is communication infrastructurefor future multi-core Systems-on-Chip (SoCs). NoCsare expected to overcome scalability and performancelimitations of Point-to-Point (P2P) and bus-basedcommunication systems. The routing algorithm of agiven NoC affects the performance of the systemmeasured with respect to metrics such as latency,throughput and load distribution. In this work, thepopular Orthogonal One Turn (O1TURN) and DimensionOrder Routing algorithms (DOR) for 2D-meshes areimplemented by computer simulation. Investigation ofthe effect of parameters such as packet, buffer, a...
Network-on-Chip (NoC) is communication infrastructure
for future multi-core Systems-on-Chip (SoCs). NoCs
are expected to overcome scalability and performance
limitations of Point-to-Point (P2P) and bus-based
communication systems. The routing algorithm of a
given NoC affects the performance of the system
measured with respect to metrics such as latency,
throughput and load distribution. In this work, the
popular Orthogonal One Turn (O1TURN) and Dimension
Order Routing algorithms (DOR) for 2D-meshes are
implemented by computer simulation. Investigation of
the effect of parameters such as packet, buffer, and
topology sizes on the performance of the network
showed that the center of the network is loaded more
than the edges. A DOR algorithm with modified flit
injection policy is evaluated to achieve a more
balanced load distribution. This book explains basic
concepts of On-Chip Networks and can be used as an
introductory material.
for future multi-core Systems-on-Chip (SoCs). NoCs
are expected to overcome scalability and performance
limitations of Point-to-Point (P2P) and bus-based
communication systems. The routing algorithm of a
given NoC affects the performance of the system
measured with respect to metrics such as latency,
throughput and load distribution. In this work, the
popular Orthogonal One Turn (O1TURN) and Dimension
Order Routing algorithms (DOR) for 2D-meshes are
implemented by computer simulation. Investigation of
the effect of parameters such as packet, buffer, and
topology sizes on the performance of the network
showed that the center of the network is loaded more
than the edges. A DOR algorithm with modified flit
injection policy is evaluated to achieve a more
balanced load distribution. This book explains basic
concepts of On-Chip Networks and can be used as an
introductory material.
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