Minimization of Dynamic Power Through Structural Changes &Vt Techniques
low power cmos circuits
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Over the past decade, low power, energy efficient Very Large Scale Integration design has been the focal point for active research and development. The rapid technology scaling, growing integration capacity and leakage power dissipation are the contributing factors for increas in the complexity of modern VLSI design. Voltage scaling is one of the most efficient ways for reducing power and energy in VLSI circuitry. Due to the reduced threshold voltage, switching speed becomes faster, active leakage current is increased. A technique to dynamically manage active leakage current, which reduces the...
Over the past decade, low power, energy efficient Very Large Scale Integration design has been the focal point for active research and development. The rapid technology scaling, growing integration capacity and leakage power dissipation are the contributing factors for increas in the complexity of modern VLSI design. Voltage scaling is one of the most efficient ways for reducing power and energy in VLSI circuitry. Due to the reduced threshold voltage, switching speed becomes faster, active leakage current is increased. A technique to dynamically manage active leakage current, which reduces the energy dissipation in VLSI circuitry at different circuits with different levels of complexity is required. As technology scale into the deep sub micron technology regime, sub threshold leakage power increases exponentially with the reduction of the threshold voltage. Therefore effective leakage and dynamic power minimization techniques become necessary. Ground, power and hybrid gated techniques are proposed as effective circuit level techniques that get better performance, low leakage and low dynamic power. The design and performance evaluation of 1-bi.
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