Microdot: A Four-Bit Microcontroller Designed for Distributed Low-End Computing in Satellites
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As satellites become more complex, the on-board processing capabilities must keep up. Many satellites are an integrated collection of sensors and actuators with many requiring dedicated real-time control to operate correctly. For single processor systems, adding more sensors requires an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors are more costly and consume more power, which can tax a satellite's power resources and may lead to shorter satellite lifetimes. Commercial-Off-The-Shelf (COTS) electronic components ar...
As satellites become more complex, the on-board processing capabilities must keep up. Many satellites are an integrated collection of sensors and actuators with many requiring dedicated real-time control to operate correctly. For single processor systems, adding more sensors requires an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors are more costly and consume more power, which can tax a satellite's power resources and may lead to shorter satellite lifetimes. Commercial-Off-The-Shelf (COTS) electronic components are usually not acceptable for satellite design because they have not been hardened against the radiation environment of space. An alternative design approach is to use a distributed network of small and low power microcontrollers designed for space to handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is presented. The design is based on previous research completed at the Space Electronics Branch, Air Force Research Laboratory (AFRL/VSSE) at Kirtland AFB, NM, and the Air Force Institute of Technology at Wright- Patterson AFB, OH. The Microdot has 29 instructions and a 1K x 4 instruction memory. The distributed computing architecture is based on the Philips Semiconductor I2C Serial Bus Protocol. A prototype was implemented and tested using an Altera Field Programmable Gate Array (FPGA). The prototype was operable up to 9.1 MHz. The design was also targeted for fabrication using a radiation-hardened-by-design gate-array library from Mission Research Corporation. The gate-array library is designed for the TSMC 0.35 micrometer CMOS process.
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