Vaibbhav Taraate

Gebundenes Buch

Logic Synthesis and SOC Prototyping

RTL Design using VHDL

Beschreibung

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

Autor

Vaibbhav Taraate is Entrepreneur and Mentor at "1 Rupee S T". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Produktdetails

• Verlag: Springer / Springer Nature Singapore / Springer, Berlin
• Artikelnr. des Verlages: 978-981-15-1313-8
• 1st edition 2020
• Seitenzahl: 272
• Erscheinungstermin: 30. Januar 2020
• Englisch
• Abmessung: 241mm x 160mm x 20mm
• Gewicht: 593g
• ISBN-13: 9789811513138
• ISBN-10: 9811513139
• Artikelnr.: 57873516