Leakage Current and Ground Bounce Noise Aware MTCMOS Techniques
Multi-Threshold CMOS Techniques for Combinational Circuit Designs
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As technology is continuously scaling down leakage current is increasing exponentially. Contribution of leakage current is around 50% to the total operational power of digital circuits. With increasing demand of portable battery operated devices like cell phones, pagers and laptops, low power design has become important design style for future battery powered devices. This exponential increase in leakage power has made Multi-Threshold CMOS (MTCMOS) technique an attractive design choice for low power application. Conventional MTCMOS techniques for minimizing leakage current gives rise to ground...
As technology is continuously scaling down leakage current is increasing exponentially. Contribution of leakage current is around 50% to the total operational power of digital circuits. With increasing demand of portable battery operated devices like cell phones, pagers and laptops, low power design has become important design style for future battery powered devices. This exponential increase in leakage power has made Multi-Threshold CMOS (MTCMOS) technique an attractive design choice for low power application. Conventional MTCMOS techniques for minimizing leakage current gives rise to ground bounce noise during mode transition which is also an important challenge and reduces the reliability of the circuit. In this work different multi-threshold CMOS techniques have been presented and compared which uses the concept of forward body biasing, diode connected MOS, ultra low power diode and signal stepping.Proposed designs has shown significant improvement in ground bounce noise andstandby leakage current as compared to designs proposed in past.
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