Interfacing Techniques for SoCs with Multiple Clock Domains (MCD)
To Address the Challenges in Modern Deep Sub-Micron Technologies
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This book initially provides quantitative analysis of the severity of timing constraints associated with global synchrony in modern DSM technologies. Then it shows that different processing elements may work in different clock domains to alleviate these constraints, hence giving rise to MCDs in SoC. Modules in such SoCs are mutually asynchronous and these systems are called as Globally Asynchronous Locally Synchronous (GALS). Some interfacing strategy is required to communicate these mutually asynchronous elements. The asynchronous GALS interfaces are conventionally described at the RTL or sys...
This book initially provides quantitative analysis of the severity of timing constraints associated with global synchrony in modern DSM technologies. Then it shows that different processing elements may work in different clock domains to alleviate these constraints, hence giving rise to MCDs in SoC. Modules in such SoCs are mutually asynchronous and these systems are called as Globally Asynchronous Locally Synchronous (GALS). Some interfacing strategy is required to communicate these mutually asynchronous elements. The asynchronous GALS interfaces are conventionally described at the RTL or system level. Hence crosstalk glitches susceptibility cannot be addressed at protocol development stage. This work contributes in identifying, modeling and quenching these crosstalk glitches using an analytical modeling technique. The proposed technique provides basis of a framework to the designer to verify the asynchronous protocols against crosstalk glitches at behavioral level. In the last part of the book loosely synchronous interfacing strategies are discussed. Some new techniques are introduced that alleviates the clock skew using novel clock scheduling techniques.
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