Instruction generation for cache resident self test of processors
Targeting both stuck-at and delay faults in processors and SOCs
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With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for def...
With delay defects becoming more common due to the properties of the newer process technologies, at- speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode (or cache resident) testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache (and also made cache resident) to test the processor for defects. Generally, only random instructions are used in native mode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. In this book, an automatic technique is proposed that alleviates the need for such manual effort.
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