Improved performance of on-chip data interconnects

Improved performance of on-chip data interconnects

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Trading off the reliability, crosstalk delay and power dissipation on on-chip buses are challenging issue for the design community in Deep Sub Micron (DSM) and very deep beneath Micron Technologies (VDSM). To improve the overall system performance it is necessary to reduce and scaling technology to control these effects data on-chip interconnects. Error Correcting Codes (ECC) have been used on the data buses to increase the reliability of the data transfer on the bus on-chip data with penalty of overhead power, delay and area. The dynamic power dissipation of interconnects depends on supply vo...