Impoved Test Techniques for Network-on-Chip Based Memory Systems
Bibhas Ghoshal
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Impoved Test Techniques for Network-on-Chip Based Memory Systems

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The search for a cost effective interconnect architecture and increasing communication demand in Systems-on-Chip (SoC) designs have paved the route to Network-on-Chip (NoC) research a decade back. However, like all other designs, NoC based SoC designs must also be tested for defects. The research on different test techniques for NoC based systems suggest that focus has been primarily on finding improved test techniques for NoC based logic cores. However, the embedded memory content in NoC based systems have increased over the years and will continue to increase. Due to their high density, thes...