Impact of Dynamic Voltage Scaling on Nano-Scale Circuit Optimization
45-nm CMOS Technology
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Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under...
Circuit designers perform optimization procedures targeting speed and power. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques applied to the circuit at a fixed voltage. DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during optimization at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during optimization? 2) Does DVS impose any restrictions to design-time circuit optimizations? This is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow for ISCAS 85 c432. Results showed that we should not optimize using Dual-VT at an arbitrary voltage but at the lowest in the DVS range, otherwise non-critical paths might become critical paths at run-time.
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