Koen De Bosschere / David Kaeli / Per Stenström / David Whalley / Theo Ungerer (eds.)

High Performance Embedded Architectures and Compilers

Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007. Proceedings
Herausgegeben:Whalley, David; Bosschere, Koen De; Kaeli, David

• Broschiertes Buch

Produktbeschreibung

This book constitutes the refereed proceedings of the Second International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2007, held in Ghent, Belgium, in Januar 2007.
The 19 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on secure and low-power embedded memory systems, architecture/compiler optimizations for efficient embedded processing, adaptive microarchitectures, architecture evaluation techniques, generation of efficient embedded applications, as well as optimizations and architectural tradeoffs for embedded systems.

Produktdetails

• Theoretical Computer Science and General Issues 4367
• Verlag: Springer / Springer Berlin Heidelberg / Springer, Berlin
• Artikelnr. des Verlages: 978-3-540-69337-6
• Seitenzahl: 307
• Englisch
• Abmessung: 17mm x 155mm x 235mm
• Gewicht: 504g
• ISBN-13: 9783540693376
• ISBN-10: 3540693378
• Artikelnr.: 22514822

Inhaltsangabe

Invited Program.- Keynote: Insight, Not (Random) Numbers: An Embedded Perspective.- I Secure and Low-Power Embedded Memory Systems.- Compiler-Assisted Memory Encryption for Embedded Processors.- Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems.- Applying Decay to Reduce Dynamic Power in Set-Associative Caches.- II Architecture/Compiler Optimizations for Efficient Embedded Processing.- Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.- Bounds Checking with Taint-Based Analysis.- Reducing Exit Stub Memory Consumption in Code Caches.- III Adaptive Microarchitectures.- Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.- Fetch Gating Control Through Speculative Instruction Window Weighting.- Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches.- Branch History Matching: Branch Predictor Warmup for Sampled Simulation.- Sunflower : Full-System, Embedded Microarchitecture Evaluation.- Efficient Program Power Behavior Characterization.- Generation of Efficient Embedded Applications.- Performance/Energy Optimization of DSP Transforms on the XScale Processor.- Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms.- A Throughput-Driven Task Creation and Mapping for Network Processors.- Optimizations and Architectural Tradeoffs for Embedded Systems.- MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization.- Evaluation of Offset Assignment Heuristics.- Customizing the Datapath and ISA of Soft VLIW Processors.- Instruction Set Extension Generation with Considering Physical Constraints.