High-Performance and Low-Power Network on Chip Switch
Network on Chip
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Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). Two power reduction techniques are exploited to design the proposed switch. The proposed NoC switch employs power supply gating to reduce the power dissipation. Adaptive virtual channel (AVC) is proposed as a novel technique to reduce power dissipation of the NoC switch. AVC technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating reduces the average leakage power consumption of proposed switch. The proposed techni...
Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). Two power reduction techniques are exploited to design the proposed switch. The proposed NoC switch employs power supply gating to reduce the power dissipation. Adaptive virtual channel (AVC) is proposed as a novel technique to reduce power dissipation of the NoC switch. AVC technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating reduces the average leakage power consumption of proposed switch. The proposed techniques reduce the leakage and dynamic power dissipation of the switch.
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