High-Accuracy CMOS Smart Temperature Sensors
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This book describes the theory and design of high-accuracy CMOS smart temperature sensors. The major topic of the work is the realization of a smart temperature sensor that has an accuracy that is so high that it can be applied without any form of calibration. Integrated in a low-cost CMOS technology, this yields at the publication date of this book one of the most inexpensive intelligent general purpose temperature sensors in the world. The first thermometers could only be read by the human eye. The industrial revolution and the following computerization asked for more intelligent sensors, wh...
This book describes the theory and design of high-accuracy CMOS smart temperature sensors. The major topic of the work is the realization of a smart temperature sensor that has an accuracy that is so high that it can be applied without any form of calibration. Integrated in a low-cost CMOS technology, this yields at the publication date of this book one of the most inexpensive intelligent general purpose temperature sensors in the world. The first thermometers could only be read by the human eye. The industrial revolution and the following computerization asked for more intelligent sensors, which could easily communicate to digital computers. This led to· the development of integrated temperature sensors that combine a bipolar temperature sensor and an A-to-D converter on the same chip. The implementation in CMOS technology reduces the processing costs to a minimum while having the best-suited technology to increase the (digital) intelligence. The accuracy of conventional CMOS smart temperature sensors is degraded by the offset of the read-out electronics. Calibration of these errors is quite expensive, however, dynamic offset-cancellation techniques can reduce the offset of amplifiers by a factor 100 to 1000 and do not need trimming. Chapter two gives an elaborate description of the different kinds of dynamic offset-cancellation techniques. Also a new technique is introduced called the nested chopper technique. An implementation of a CMOS nested-chopper instrumentation amplifier shows a residual offset of less than lOOn V, which is the best result reported to date.
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