Hardware-Software Coverification of Programmable SOCs
Verification tips and tricks
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With gate counts and system complexity growing rapidly, engineers have to find efficient ways of designing hardware integrated circuits. The advent of hardware description languages and synthesis methodologies improved designer productivity by raising the abstraction level. However, there is still a growing productivity gap between the number of transistors-per-chip that can be fabricated and the transistors-per-designer that can be effectively designed and verified. Various kinds of Intellectual Property cores are now widely available and are used in making ICs. These Systems on a chip (SOCs)...
With gate counts and system complexity growing rapidly, engineers have to find efficient ways of designing hardware integrated circuits. The advent of hardware description languages and synthesis methodologies improved designer productivity by raising the abstraction level. However, there is still a growing productivity gap between the number of transistors-per-chip that can be fabricated and the transistors-per-designer that can be effectively designed and verified. Various kinds of Intellectual Property cores are now widely available and are used in making ICs. These Systems on a chip (SOCs) generally contain a microprocessor as one of their IP cores in order to make them flexible. It is widely estimated that between 60%-80% of the design effort is dedicated to verification with almost half of that time spent in construction and debugging of the simulation environments. This book describes the building of a Programmable Wireless Receiver SOC using hardware-software coverification techniques. The CPU used is open-source, making it appropriate for teaching SOC verification as part of a university curriculum. The book can be used as a guideline for designing CPU-based SOCs.
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