Hardware Implementation of Digital Satellite Receiver
Digital Receiver on FPGA
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As continual research is being conducted in the area of Digital System Design and Digital Communication, one of the most practical applications under vigorous development is in the design and implementation of a high speed digital satellite receiver. While the problem of forward error correction at high data rates under gross variations remains somewhat unsolved, the present project is a vivid demonstration of efficient system design and algorithms in the field of high speed digital satellite receivers. A receiver system capable of reliable forward error correction of seven symbols, with reduc...
As continual research is being conducted in the area of Digital System Design and Digital Communication, one of the most practical applications under vigorous development is in the design and implementation of a high speed digital satellite receiver. While the problem of forward error correction at high data rates under gross variations remains somewhat unsolved, the present project is a vivid demonstration of efficient system design and algorithms in the field of high speed digital satellite receivers. A receiver system capable of reliable forward error correction of seven symbols, with reduced constraints in regards to high speed sampling and FPGA based hardware utilization has been implemented. The design of the digital receiver system consists of the various modules which implement the different successive steps in digital communication a Digital Front End, Hilbert Transformer, Timing and Phase Recovery, and a Reed Solomon Decoder for forward error correction. These modules were tested on simulated input, and their synthesized hardware instances were then tested on the FPGA using a PC interface with ChipScope.
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