FPGA Implementation of Speech Recognition System Based on HMM
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This book introduced an approach to design and implement an embedded SoPC (System on Programmable Chip) technique with Altera Nios II processor on a FPGA chip for real-time speech recognition system by developing hardware/software with minimum usage of resources (hardware components) and relatively small size software. This reduces the memory utilization, achieved by using Mel Frequency Cepstral Coefficients (MFCCs) technique as feature extraction combined with its first derivative ( MFCCs) including power computation of the speech frames (i.e. E,MFCC, E,and MFCC), called observation vector of...
This book introduced an approach to design and implement an embedded SoPC (System on Programmable Chip) technique with Altera Nios II processor on a FPGA chip for real-time speech recognition system by developing hardware/software with minimum usage of resources (hardware components) and relatively small size software. This reduces the memory utilization, achieved by using Mel Frequency Cepstral Coefficients (MFCCs) technique as feature extraction combined with its first derivative ( MFCCs) including power computation of the speech frames (i.e. E,MFCC, E,and MFCC), called observation vector of the speech signal. To model the obtained observation, Gaussian Mixture Model (GMM) has been used, which is passed to a Hidden Markov Model (HMM) as probabilistic model to process the GMM statistically to take a decision on the uttered words recognition, whether a single or composite, one or more syllable words (i.e. one, six, welcome). The words that are used for training and testing the system included selected English and Arabic words.
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