Efficient Yield Estimation Techniques On Analog Design Automation Tool
Versandfertig in 6-10 Tagen
24,99 €
inkl. MwSt.
PAYBACK Punkte
12 °P sammeln!
With the improvements in fabrication processes, electronic circuit designers have begun to design complex circuits which consist of multibillion transistors. But, as circuit complexity increases, the silicon complexity also increases, leading to process variations having a profound effect on the circuit performance especially in sub micron technologies. Therefore, even if a circuit was designed to achieve a certain design specification, there will be a discrepancy between the simulated and the measured performances. This difference can lead to a decrease in the yield. Circuit designers tend to...
With the improvements in fabrication processes, electronic circuit designers have begun to design complex circuits which consist of multibillion transistors. But, as circuit complexity increases, the silicon complexity also increases, leading to process variations having a profound effect on the circuit performance especially in sub micron technologies. Therefore, even if a circuit was designed to achieve a certain design specification, there will be a discrepancy between the simulated and the measured performances. This difference can lead to a decrease in the yield. Circuit designers tend to handle this problem by leaving a safety margin; however, this leads to overdesign and loss of precious chip area. Therefore, there is an undeniable need to have efficient design automation tools for reducing design time without compromising performance. Cross entropy minimization based on importance sampling (IS) method is chosen for the scope of this work due to its efficiency, although there are lots of different Monte Carlo based proposals. Also, a hybrid Quasi-Monte Carlo method has been utilized in order to both select rare event threshold that is needed for cross entropy based algorithm.
Andere Kunden interessierten sich für
