Efficient Test Data Compression and Fault Analysis in VLSI Circuits
Sivaganesan Subramaniam
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Efficient Test Data Compression and Fault Analysis in VLSI Circuits

Test Data Compression and Decompression Using Efficient Bitmask and Dictionary Selection Method

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In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then de...