Efficient Hardware Implementation of an Advanced Turbo Decoder
An ASIC Implementation
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Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in paramet...
Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleaver in the presence of additive white Gaussian noise, using MATLAB. The hardware of the Turbo decoder has been modelled in VHDL, simulated in VCS, synthesized using Design compiler and physical implementation has been carried out using IC Compiler.
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