DIGITAL CORE OUTPUT TEST DATA COMPRESSION ARCHITECTURE
Model, Implementation, and Analysis
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With the unprecedented growth of the electronics industry, the integration densities besides system complexities continued to increase, and hence, the need for better and more effective methods of testing to assure reliable operations of chips, which is the mainstay of today s many sophisticated devices and products, was intensely felt. Generally, the cost of testing chips is prohibitive, accounting for 35% to 55% of their total manufacturing expense. Furthermore, testing an integrated circuit is also time- consuming, taking up to about one half of the total design-cycle time. On the other han...
With the unprecedented growth of the electronics industry, the integration densities besides system complexities continued to increase, and hence, the need for better and more effective methods of testing to assure reliable operations of chips, which is the mainstay of today s many sophisticated devices and products, was intensely felt. Generally, the cost of testing chips is prohibitive, accounting for 35% to 55% of their total manufacturing expense. Furthermore, testing an integrated circuit is also time- consuming, taking up to about one half of the total design-cycle time. On the other hand, the amount of time available for manufacturing, testing, and marketing a product is constantly on the decline. Moreover, as a result of diminishing trade barriers and global competition, customers now demand products of superior quality at lower price. However, to achieve this better quality at relatively low cost, evidently, the testing strategies have to be improved. This book is a comprehensive guide to new chip testing and built-in self-test techniques that will allow students, researchers, and chip designers to master chip design for test architectures, for diagnosis of digital cores.
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