Development of Efficient Hardware Architecture for Image Compression

Development of Efficient Hardware Architecture for Image Compression

The Mapping of the Computational Tasks Associated with the Discrete Wavelet Transform DWT

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Focusing on the intensive computations involved in the discrete wavelet transform (DWT), the design of efficient hardware architectures for a fast computation of the transform has become imperative, especially for real-time applications. With this overall objective, the mapping of the computational tasks associated with the various resolution levels of the 5/3 DWT is first mathematically modeled, and then a modified computation of the DWT stages are explored from the standpoint of evading computing high frequency subbands. Furthermore, a Haar wavelet transform (HWT) is used for comparison. The...