Designing Network On-Chip Architectures in the Nanoscale Era
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"Paving the way for the use of network on-chip architectures in 2015 platforms, this book presents the industrial requirements for such long-term platforms as well as the main research findings for technology-aware architecture design. It covers homogeneous design techniques and guidelines, including the solutions that are most appealing to the industry and best suited to meet the requirements of on-chip integration. Each chapter deals with a specific key architecture design, including fault tolerant design, topology selection, dynamic voltage and frequency scaling, synchronization, network on-chip resources exposed to the architecture, routing algorithms, and collective communication"--
A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs-consistently focusing on topics most pertinent to real-world NoC designers. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues. They also explore the latest trends, such as vertical integration and variation-tolerant design.
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