Design Techniques Towards a Full-Rate
Ahmad Yazdi
Broschiertes Buch

Design Techniques Towards a Full-Rate

40Gb/s Transmitter in 0.18µm CMOS

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We investigate high-speed design techniques that enable realization of a full-rate broadband serializer operating at 40Gb/s using a 0.18µm CMOS process. Bandwidth enhancement techniques, including shunt-peaking and multi-pole band-width enhancement, have been incorporated in the di erent high speed blocks in the serializer. Different inductor structures have been studied and appropriately incorporated for bandwidth enhancement and resonating circuits, consistent with various constraints on speed, quality factor, and chip area. A novel dynamic re-timing circuit capable of clocked 40GHz operati...