Design Space Exploration of Network-on-Chip at System level
Rabindra Kumar Jena
Broschiertes Buch

Design Space Exploration of Network-on-Chip at System level

A Genetic Algorithm Approach

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About the Book: The goal of this text is to help students, researchers and academicians, who are working in the field of CAD for VLSI. Network-on-Chip(NoC) has been recently developed as an on-chip communication solution for System-on-Chip(SoC) design. This paradigm supports various communication resources at a time and overcomes the limitations of bus-based System. Design space exploration methodology at system level reduces the time-to-market pressure of the large and complex systems. On the other hand, design space exploration at system level is a combinatorial optimization problem. So, mul...