Design of Proposed Hybrid 128-bit Parallel Adder/Subtractor
JOSEPH ANTHONY PRATHAP
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Design of Proposed Hybrid 128-bit Parallel Adder/Subtractor

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The book explains about the transistor level design of novel parallel adder/subtractor using the 45 nm technology in cadence tool. The proposed novel parallel 128-bit Adder/Subtractor is utilized in the design of parallel adder/ subtractor with the resolution up to 27 bits. Though there are several design technologies like static CMOS logic, Dynamic CMOS, CPL, Transmission Gate Array, the proposed design is advantageous for minimized chip area, low power consumption and high speed of operation. In this work, two circuit topologies are proposed by utilizing the 8T and 12T XOR CMOS design for th...