Design of Low Power High Speed Level Shifters For Multi VDD Systems
Srinivasulu Gundala
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Design of Low Power High Speed Level Shifters For Multi VDD Systems

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The power consumption and speed performance of VLSI circuits can be optimised by number methodologies, the methodologies which involve power supply voltage reduction is consider as effective and efficient technique, as decreases in power supply voltage leads to reduction of speed performance and power consumption of the VLSI design. The best approach called as Clustered Voltage Scaling, means sectoring the entire design into different voltage blocks or islands and all high-speed sensitive blocks are operated with core voltage VDDH to attain the speed performance and low-speed sensitive blocks ...