Design and Development of Low Voltage Process Invariant SRAM Cell
SRAM Cell Design Procedure
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Low read stability and high leakage current are two major problems in Static Random-Access Memory (SRAM) at the scaled CMOS technology node. This Book provides stability, leakage and process variation analysis of a Schmitt Trigger and read buffer based differential 10T (hereafter called ST3) SRAM cell. The ST3 cell provides improve read stability, tight Read Static Noise Margin (RSNM) distribution due to simultaneously implementation of Schmitt trigger and read buffer technique. Moreover, ST3 cell consumes low leakage current because of stack transistor technique and higher process tolerance d...
Low read stability and high leakage current are two major problems in Static Random-Access Memory (SRAM) at the scaled CMOS technology node. This Book provides stability, leakage and process variation analysis of a Schmitt Trigger and read buffer based differential 10T (hereafter called ST3) SRAM cell. The ST3 cell provides improve read stability, tight Read Static Noise Margin (RSNM) distribution due to simultaneously implementation of Schmitt trigger and read buffer technique. Moreover, ST3 cell consumes low leakage current because of stack transistor technique and higher process tolerance due to simultaneously implantation of Schmitt trigger and read buffer techniques. This ST3 cell may be an attractive choice for battery-operated applications such as implantable medical device and remote sensor at the nm technology node.
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