DELOTS Algorithm For Nano Digital Circuits:Design And Optimization
Low Power - High Performance Digital Circuits Based On Transistor Sizing In Nanotechnology Era
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In This Book, a new approach for optimizing the Power Delay Product (PDP) of any digital circuit is proposed. The new approach selects the optimal width size of transistor to enhance the circuit performance (Delay) and reduce the circuit power dissipation (leakage). For this purpose, the new approach is hierarchal composed of three models; Graph Model (GM) for generating a directed graph to describe the relation between all the objects in the circuits: Inputs, Outputs, type of transistor (p-Mos, n-Mos), VDD, GND, and all the paths from any input to any output. Mathematical Model (MM) as a prer...
In This Book, a new approach for optimizing the Power Delay Product (PDP) of any digital circuit is proposed. The new approach selects the optimal width size of transistor to enhance the circuit performance (Delay) and reduce the circuit power dissipation (leakage). For this purpose, the new approach is hierarchal composed of three models; Graph Model (GM) for generating a directed graph to describe the relation between all the objects in the circuits: Inputs, Outputs, type of transistor (p-Mos, n-Mos), VDD, GND, and all the paths from any input to any output. Mathematical Model (MM) as a prerequisite stage that produced two levels of transistor width where will be used later for PDP optimization. Finally, the Heuristic Model (HM), which uses A as Artificial intelligent (AI) heuristic searching algorithm to find the suitable level of transistor width to achieve the maximum PDP optimization. All the measurements and tests for the new approach have been performed under 22 m BSIM4 Foundries predictive model. The average improvement in PDP was 43 % for cascading full adder and 38% for ISCAS C17 Benchmark.
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