Decimation Lowpass Filters for SIGMA-DELTA Modulators - A Comparative Study
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Master's Thesis from the year 1998 in the subject Electrotechnology, grade: 1,0 (A), University of Rhode Island (--), language: English, abstract: The purpose of this thesis is to compare several filter topologies used for the decimation of sigma-delta modulated digital signals. The goal is to present optimized filter architectures with regard to an efficient VLSI implementation. A fifth-order 1-bit sigma-delta modulator using local feedback techniques will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 32. The decimation fi...
Master's Thesis from the year 1998 in the subject Electrotechnology, grade: 1,0 (A), University of Rhode Island (--), language: English, abstract: The purpose of this thesis is to compare several filter topologies used for the decimation of sigma-delta modulated digital signals. The goal is to present optimized filter architectures with regard to an efficient VLSI implementation. A fifth-order 1-bit sigma-delta modulator using local feedback techniques will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 32. The decimation filter must guarantee a narrow transition band between 0.5 and 0.55 and stopband attenuation of 100dB.Chapter 1 provides a brief introduction into the principles of digital signal processing. The considerations are focused on FIR filters due to the requirements for acoustic applications. Chapter 2 illustrates the proposed overall structure and the design flow.The objective of chapter 3 is to present the principles of oversampling data converters using sigma-delta techniques. The 5V fifth-order SigmaDelta-modulator with 90dB dynamic range (SNR+THD) will be presented, which has been fabricated in 1.2$um CMOS technology. For the sake of simplicity and robustness, a 1-bit quantizer will be used.Chapter 4 deals with typical hardware realizations of digital filters. Apart from the ``brute force'' implementation of the multirate filter with identical filters running in parallel, also the LUT-based approach for small filter orders will be presented. Due to the advantages of compact implementation, the bit-serial approach and the bit-serial multiplier are investigated in detail.In chapter 5 the straightforward one-stage multirate FIR filter will be introduced. To satisfy the specifications, a 4096 tap lowpass FIR filter will be designed. The influence of coefficient quantization is investigated and furthermore the ``block scaling'' method, to represent small values, is presented. The single-stage implementation becomes the more unattractive the higher the filter specifications are.Chapter 6, therefore, focuses the investigations on cascaded structures. The first stage is realized as a comb or $sinc^K$ filter and decimates by a factor of 8 or 4. The frequently used conventional comb filter will be used but also a new architecture will be described. The new structure is based on the conventional comb filter with filter sharpening techniques to improve the frequency behavior. The unavoidable passband droop must be compensated for by the following lowpass FIR filter.
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