CMOS VLSI Layout and Verification of a SIMD Computer
Jianqing Zheng
Broschiertes Buch

CMOS VLSI Layout and Verification of a SIMD Computer

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A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed. This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it. This work was reproduced from the original artifact, and remains as true to the original work as possib...