Assisting Abstraction and Verification of Hardware Intellectual Property (Ip) Modules
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Hardware verification has become challenging due to growing complexity of today's designs. We aim at assisting verification of hardware intellectual properties (IP) at register transfer level by means of data abstraction and static formal analysis techniques. We intuitively define the "Control". The proposed definition was envisaged for separating Control and Data, independent of the subjective choice or the specific syntax. We have worked around a few semantic issues of the definition and demonstrated by reasoning. A control-data slicing algorithm is proposed to split the module into a contro...
Hardware verification has become challenging due to growing complexity of today's designs. We aim at assisting verification of hardware intellectual properties (IP) at register transfer level by means of data abstraction and static formal analysis techniques. We intuitively define the "Control". The proposed definition was envisaged for separating Control and Data, independent of the subjective choice or the specific syntax. We have worked around a few semantic issues of the definition and demonstrated by reasoning. A control-data slicing algorithm is proposed to split the module into a control slice and a data slice. An abstraction is achieved in case of slicing with data-independent control. The bit accurate RTL data slice is replaced by a functional data computation model for fast simulations. The control slice being critical entity with timing information, remains intact during this process. We have proposed the notion of significance to represent the intentional data in IP modules. Significance is used to represent boolean data dependencies in modules for formal verification of the data flows.
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