Against the Power Wall
Floorplanning and Interconnecting on Chips
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Computer performance has been growing at an exponential rate, in its golden age, driven by the Moore's law of manufacturing technology and the advancement of computer architecture. However, the growth rate has been hit by a 'power wall' due to the physical limit on heat dissipation of silicon chips. As a result, reducing power consumption has become a focusing target for computer architects and circuit designers. In this book, we discuss two topics around this target, both on how to reduce the power for inter-communications inside the chip. The first and most direct way is to shorten the inter...
Computer performance has been growing at an exponential rate, in its golden age, driven by the Moore's law of manufacturing technology and the advancement of computer architecture. However, the growth rate has been hit by a 'power wall' due to the physical limit on heat dissipation of silicon chips. As a result, reducing power consumption has become a focusing target for computer architects and circuit designers. In this book, we discuss two topics around this target, both on how to reduce the power for inter-communications inside the chip. The first and most direct way is to shorten the interconnect lengths, which is possible considering current chips are made of a single layer of circuits. If we build them in multiple layers, like multi-store buildings, we have a much smaller foot print, reducing interconnect distances. The second way, if the distances are already determined, is to minimize wires involved in communication actions. Given the floorplan, how to set up the wiring to enable point-to-point communications under minimum power? Both difficulties and opportunities are revealed, and both await further explorations.
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