Advanced HDL Synthesis and SOC Prototyping
Vaibbhav Taraate
Gebundenes Buch

Advanced HDL Synthesis and SOC Prototyping

RTL Design Using Verilog

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This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describ...