A Phase Locked Loop Based Integer N Frequency Synthesizer
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The present work describes about a phase locked loop (PLL) based integer n frequency synthesizer for unlicensed national information infrastructure (UNII) lower band. It covers a frequency range of 5.15 - 5.25 GHz which is used by IEEE 802.11a. For simplification of design, the channel spacing of the frequency synthesizer is taken to be 5 MHz. The frequency synthesizer consists of a phase frequency detector (PFD), a charge pump (CP), a second order loop filter (LP), a voltage controlled oscillator (VCO) and a programmable divider block (PD). The dual modulus prescaler based programmable divide...
The present work describes about a phase locked loop (PLL) based integer n frequency synthesizer for unlicensed national information infrastructure (UNII) lower band. It covers a frequency range of 5.15 - 5.25 GHz which is used by IEEE 802.11a. For simplification of design, the channel spacing of the frequency synthesizer is taken to be 5 MHz. The frequency synthesizer consists of a phase frequency detector (PFD), a charge pump (CP), a second order loop filter (LP), a voltage controlled oscillator (VCO) and a programmable divider block (PD). The dual modulus prescaler based programmable divider is used for the frequency synthesizer purpose because it is the most popular technique due to its versatility and facility of implementation. All the frequency synthesizer components are modeled using SIMULINK environment. The frequency synthesizer performance is simulated in terms of Root locus, step response and Bode plot methods using MATLAB in order to check the correct transfer function and stability. Simulation results of the integer frequency synthesizer confirm the validation of the model.
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