A Novel LVSD Design and its Robustness to Process Variation Effects
Low Power and Robust Techniques for CMOS Circuits
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Due to the aggressive scaling in the IC design, interconnect delay has adversely been affected, which subsequently reduces the performance. This problem can be mitigated by employing line drivers but they have high power consumption. Low-swing signalling techniques can provide high-speed signalling with low-power consumption, and most schemes are immune to noise as they have good signal-to-noise-ratio (SNR). However, they tend to have large area penalty and complexity as they require additional circuitry. A diode-connected driver circuit has the best attributes over other drivers in terms of l...
Due to the aggressive scaling in the IC design, interconnect delay has adversely been affected, which subsequently reduces the performance. This problem can be mitigated by employing line drivers but they have high power consumption. Low-swing signalling techniques can provide high-speed signalling with low-power consumption, and most schemes are immune to noise as they have good signal-to-noise-ratio (SNR). However, they tend to have large area penalty and complexity as they require additional circuitry. A diode-connected driver circuit has the best attributes over other drivers in terms of low power, low delay, good SNR and low area-overhead. By incorporating a diode-connected configuration at the output, it can provide a high-speed signalling due to its high-driving capability. However, this configuration also has its limitations due to its inept adaptability to process variations, as well as leakage currents. To address these limitations, two novel driver schemes have been designed, where they have significant improvement in terms of delay, power consumption, noise and robustness against PVT effect and external disturbances such as crosstalk and single-event-upsets.
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