1 Bit Full Adder Cell for reducing low leakage current
VLSI
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As technology scales into the nanometer regime leakage current, active power, delay and area are the important metric for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell are proposed for mobile applications and a novel technique has been introduced with improved staggered phase damping technique and also Gated Diffusion Input (GDI) technique for further reduction in the Active power. Leakage power is being estimated when the circuits are connected with a sleep transistor, Further compared to the Base case and Design1 and Design2 and...
As technology scales into the nanometer regime leakage current, active power, delay and area are the important metric for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cell are proposed for mobile applications and a novel technique has been introduced with improved staggered phase damping technique and also Gated Diffusion Input (GDI) technique for further reduction in the Active power. Leakage power is being estimated when the circuits are connected with a sleep transistor, Further compared to the Base case and Design1 and Design2 and GDI Technique when a circuit is connected to sleep transistor. We introduced a new transistor resizing approach for 1bit full adder cells to determine the optimal sleep transistor size which reduce the leakage power and Area. The simulation results depicts that the proposed design also leads to efficient 1bit full adder cells in terms of standby leakage power, active power. We have performed simulations using Microwind 90nm standard CMOS technology at room temperature with supply voltage of 1V.
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