Nisar Ahmed

Nanometer Technology Designs

High-Quality Delay Tests

• Broschiertes Buch

Produktbeschreibung

Adopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timing-related defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuck-at fault test alone cannot ensure a high quality level of chips. At-speed tests using the transition fault model has become a requirement in technologies below 180nm.

Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IR-drop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes newtechniques and methodologies to improve the overall quality of the transition fault test.

Produktdetails

• Verlag: Springer / Springer US / Springer, Berlin
• Artikelnr. des Verlages: 978-1-4419-4559-4
• 2008
• Seitenzahl: 300
• Erscheinungstermin: 14. Dezember 2011
• Englisch
• Abmessung: 235mm x 155mm x 17mm
• Gewicht: 458g
• ISBN-13: 9781441945594
• ISBN-10: 1441945598
• Artikelnr.: 32136042

Inhaltsangabe

Introduction to path delay and transition delay fault models and test methods.- At-speed test challenges for nanometer technology designs.- Low-cost tester friendly design-for-test techniques.- Improving test quality of current at-speed test methods.- Functionally untestable fault list generation and avoidance.- Timing-based ATPG for screening small delay faults.- Faster-than-at-speed test considering IR-drop effects.- IR-drop tolerant at-speed test pattern generation and application.