Formal Semantics and Proof Techniques for Optimizing VHDL Models - Umamageswaran, Kothanda; Pandey, Sheetanshu L.; Wilsey, Philip A.
89,99 €
versandkostenfrei*

inkl. MwSt.
Versandfertig in 2-4 Wochen
45 °P sammeln
  • Broschiertes Buch

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Produktbeschreibung
Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
  • Produktdetails
  • Verlag: Springer, Berlin
  • Softcover reprint of the original 1st ed. 1999
  • Seitenzahl: 184
  • Erscheinungstermin: 26. Oktober 2012
  • Englisch
  • Abmessung: 235mm x 155mm x 10mm
  • Gewicht: 289g
  • ISBN-13: 9781461373315
  • ISBN-10: 146137331X
  • Artikelnr.: 37476719
Inhaltsangabe
1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.