Formal Semantics and Proof Techniques for Optimizing VHDL Models - Umamageswaran, Kothanda; Pandey, Sheetanshu L.; Wilsey, Philip A.
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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Produktbeschreibung
Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
  • Produktdetails
  • Verlag: Springer Netherlands
  • Repr. d. Ausg. v. 1998
  • Seitenzahl: 184
  • Erscheinungstermin: 30. November 1998
  • Englisch
  • Abmessung: 241mm x 160mm x 15mm
  • Gewicht: 440g
  • ISBN-13: 9780792383758
  • ISBN-10: 0792383753
  • Artikelnr.: 23080125
Inhaltsangabe
1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.