VLSI Chip Design with the Hardware Description Language VERILOG - Golze, Ulrich
62,99 €
versandkostenfrei*

inkl. MwSt.
Versandfertig in 2-4 Wochen
31 °P sammeln
    Broschiertes Buch

The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book. After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG,…mehr

Produktbeschreibung
The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.
  • Produktdetails
  • Verlag: Springer / Springer, Berlin
  • Softcover reprint of the original 1st ed. 1996
  • Seitenzahl: 376
  • Erscheinungstermin: 23. August 2014
  • Englisch
  • Abmessung: 235mm x 155mm x 20mm
  • Gewicht: 569g
  • ISBN-13: 9783642646508
  • ISBN-10: 3642646506
  • Artikelnr.: 41320700
Autorenporträt
Prof. Dr. Ulrich Golze ist Professor für den Entwurf integrierter Schaltungen an der TU Braunschweig.
Inhaltsangabe
Design of VLSI Circuits.- Design of VLSI Circuits.- RISC Architectures.- RISC Architectures.- Short Introduction to VERILOG.- Short Introduction to VERILOG.- External Specification of Behavior.- External Specification of Behavior.- Internal Specification of Coarse Structure.- Internal Specification of Coarse Structure.- Pipeline of the Coarse Structure Model.- Pipeline of the Coarse Structure Model.- Synthesis of Gate Model.- Synthesis of Gate Model.- Testing, Testability, Tester, and Testboard.- Testing, Testability, Tester, and Testboard.- Summary and Prospect.- Summary and Prospect.- HDL Models for Circuits and Architectures.- HDL Modeling with VERILOG.