CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications: Design Methodology, Analysis, and Implementation - Bourdi, Taoufik; Kale, Izzet
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Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma…mehr

Produktbeschreibung
Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones. The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.
  • Produktdetails
  • Analog Circuits and Signal Processing (ACSP)
  • Verlag: Springer Netherlands
  • Artikelnr. des Verlages: 11904571
  • 2007
  • Seitenzahl: 208
  • Erscheinungstermin: März 2007
  • Englisch
  • Abmessung: 243mm x 165mm x 27mm
  • Gewicht: 494g
  • ISBN-13: 9781402059278
  • ISBN-10: 1402059272
  • Artikelnr.: 22553380
Autorenporträt
Taoufik Bourdi, University of Westminster, London, UK / Izzet Kale, University of Westminster, London, UK
Inhaltsangabe
Preface. Nomenclature. 1. INTRODUCTION. 1.1. Introduction. 1.2. Research contribution. 2. WIRELESS COMMUNICATIONS SYSTEMS. 2.1. introduction. 2.2. The wireless lan standards. 2.3. Wireless lan transceiver systems. 3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS. 3.1. Introduction. 3.2. Phase-locked loop frequency synthesizer. 3.3. Phase-locked loop parameters. 3.4. Noise in phase-locked loops. 3.5. Fractional-N synthesizers. 3.6. RMS phase error and Error Vector Magnitude (EVM). 3.7. Conclusion. 4. SYSTEM SIMULATION OF delta-sigma-BASED FRACTIONAL-N FREQUENCY SYNTHESIZERS. 4.1. Introduction. 4.2. Phase domain model. 4.3. Synthesizer platform evaluation. 4.4. Conclusion. 5. MULTI-MODE D-S BASED FRACTIONAL-N FREQUENCY SYNTHESIZER. 5.1. Introduction. 5.2. An overview. 5.3. A Multi-Mode Multi-Standard Delta-Sigma Based PLL Synthesizer Design. 5.4. The Delta-Sigma Frequency Synthesizer Sub-Blocks Implementation. 5.5. Measured Performance of the implemented Synthesizer. 5.6. Summary and conclusion. 6. IMPROVED PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER. 6.1. Introduction. 6.2. Overview. 6.3. Delta-Sigma controlled adaptive charge pump. 6.4. Synthesizer loop calibration. 6.5. Process Calibration I/C Slew rate & RC time constant. 6.6. VCO Tuning gain calibration. 6.7. Imroved vco band switching. 6.8. Experimental Results. 6.9. Comparison with published results. 6.10. Conclusion. 7. CONCLUSIONS AND FURTHER WORK. 7.1. Conclusion. 7.2. Further work. APPENDIX A. PHASE FREQUENCY DETECTORS & CHARGE PUMPS. 1. Phase-frequency detectors. 2. Charge pump. 3. PFD/CP characteristics. B. CONTROLLED OSCILLATORS. 1. Reference oscillators. 2. Voltage controlled oscillators. C. PHASE NOISE. 1. Calculation of global phase error from L(f). 2. Phase noise and phase modulation. 3. RMS phase error from phase noise. 4. Residual FM. D. FREQUENCY DIVIDERS. 1. Reference divider. 2. Feedback divider. 3. High speed CMOS divider design. 4. Implemented CML gates. E. CODES & PROGRAMS. INDEX